The present disclosure relates to measuring time in electronic circuitry, and, in particular, to measuring the arrival time of a signal with respect to a reference clock signal.
Time-to-Digital Converters (TDC) are used in many electronic circuits to measure the time at which a specific event occurs (e.g., the time at which a specific signal arrives). One known type of TDC measures signal arrival time by charging and discharging a capacitor at two different rates. When the signalxe2x80x94whose arrival time is to be measuredxe2x80x94arrives, a control switch closes thus coupling a current source to the capacitor which is thereby charged. After a predefined number of clock signal (xe2x80x9cclockxe2x80x9d) cycles, the control switch opens, forcing a second current source to discharge the charged capacitor. The arrival time of the signal is proportional to the ratio of the currents generated by the two current sources as well as by the frequency and the number of clock cycles between the closing and opening of the control switch. The higher the ratio of the two current sources, the greater is the accuracy with which the arrival time is measured.
Although known TDCs can accurately measure the arrival time of a signal, they are slow. Assume, for instance, that the first and second current sources (discussed above) respectively generate 10 ma and 1.6 xcexca of current, yielding a current ratio of 6000. Assume further that the frequency of the reference clock is 400 MHz (i.e., the period of the clock is 50 nsec) and that the control switch opens one full clock cycle after it closes. Using the above numbers, it takes 300 xcexcsec (6,000xc3x9750 nsec) for such a TDC to measure the arrival time of a signal. The e.g. 300 xcexcsec time interval required for such time measurements is prohibitively long thus making it impossible to measure the arrival time of two signals which are e.g. less than 300 xcexcsec apart.
Accordingly, it would be advantageous to have a system and a method which can measure arrival times of successive signalsxe2x80x94separated from one another by more than one period of a reference clockxe2x80x94with a resolution finer than the period of the reference clock.
In accordance with this disclosure, a time-to-digital converter records the arrival times of successive signals which are separated from one another by more than one period of a reference clock signal. The time-to-digital converter includes among other components, a first coarse delay path which further includes N coarse delay circuits (alternatively referred to hereinbelow as coarse delay stages) connected in series; and N fine delay paths, each including (M-1) fine delay circuits (alternatively referred to as fine delay stages) connected in series to thereby provide M nodes.
The output signal of each of the N coarse delay stages in the first coarse delay path is applied to an input terminal of a different one of the fine delay paths.
The time-to-digital converter records the arrival times of successive signals with respect to a reference clock by counting the number of fine delay paths as well as the number of fine delay stages within each of the fine delay paths through which the signals propagate. The time delay across each of the N fine delay paths is equal to that across each of the coarse delay stages.
A different one of N M-bit registers is coupled to each of the M nodes of each of the fine delay paths. Each register bit stores either a 1 or a 0 depending on whether the signal to be measured propagates through the node to which the register bit is coupled.
The time-to-digital converter also includes N registered priority encoders, each coupled to a different one of the M-bit registers. Each registered priority encoder receives and performs a priority function on the M bits of the register to which it is coupled.
The time-to-digital converter also includes a coarse delay encoder coupled to each of the N registered priority encoders for determining the extent of the propagation of the signals in the coarse delay and the fine delay paths to thereby generate time stamps corresponding to the arrival times of the signals.
The arrival of the signalsxe2x80x94independent of their times of arrivalxe2x80x94are also recorded and transferred to a flag signal.
A second coarse delay path including N coarse delay stagesxe2x80x94which are also connected in seriesxe2x80x94receives the reference clock signal and generates a delayed replica of the clock signal. A phase detector maintains the clock signal and its delayed replica in phase by controlling the delay across each of the N coarse delay stages in the second coarse delay path. The clock signal leads its delayed replica by one full cycle of the clock signal.
The phase detector also maintains the delay across each of the coarse delay stages in the first and second coarse delay paths the same to thereby equalize the delay of a signal across the second coarse delay path to the period of the clock signal.
A different one of N fine delay buffers disposed between each of the N coarse delay stages in the first coarse delay path and the coarse delay stage""s associated fine delay path ensures that the delay of a signal across similarly positioned nodes of different fine delay paths is substantially the same. The delay across each fine delay path is substantially similar to the delay across a coarse delay stage.
The time-to-digital converter optionally includes 2N slave bias circuits, each receiving and supplying a signal to a different one of the coarse delay stages in each of the first and second coarse delay paths and to each of the N fine delay buffers.
In some embodiments, the time-to-digital converter operates differentially using differentially high and low signals in each of the first and second coarse delay paths, fine delay paths, the M-bit registers and the registered priority encoders.
In some embodiments of the time-to-digital converter, N is equal to 32, M is equal to 8, and signal arrival times are recorded with resolution of 5 psec using an 800 MHz clock.